Recurrence in Dense-Time AMS Assertions

The notion of recurrence over continuous or dense time, as required for expressing analog and mixed-signal behaviors, is fundamentally different from what offered by the operators SystemVerilog assertions (SVAs). This article introduces formal semantics time provides a methodology runtime verification such properties using interval arithmetic. Our property language extends SVA with real-time intervals predicates containing real-valued signals. We provide tool kit that interfaces off-the-shelf EDA tools through standard VPI.